ADDITIONAL FEATURE:  MACROCELLS INTERCONNECTED BY GLOBAL BUS; 24 MACROCELLS; 2 EXTERNAL CLOCKS

ARCHITECTURE:  PAL-TYPE

CLOCK FREQUENCY-MAX:  33.3 MHZ

JESD-30 CODE:  R-PDIP-T40

JESD-609 CODE:  E0

LENGTH:  52.4256 MM

MANUFACTURER:  ALTERA CORPORATION

MANUFACTURER PART NUMBER:  EP910PC-30

NUMBER OF DEDICATED INPUTS:  12

NUMBER OF I/O LINES:  24

NUMBER OF INPUTS:  36

NUMBER OF OUTPUTS:  24

NUMBER OF PRODUCT TERMS:  240

NUMBER OF TERMINALS:  40

OPERATING TEMPERATURE-MAX:  70 °C

OPERATING TEMPERATURE-MIN:  0 °C

ORGANIZATION:  12 DEDICATED INPUTS, 24 I/O

OUTPUT FUNCTION:  MACROCELL

PACKAGE BODY MATERIAL:  PLASTIC/EPOXY

PACKAGE CODE:  DIP

PACKAGE DESCRIPTION:  DIP, DIP40,.6

PACKAGE EQUIVALENCE CODE:  DIP40,.6

PACKAGE SHAPE:  RECTANGULAR

PACKAGE STYLE:  IN-LINE

PART PACKAGE CODE:  DIP

PBFREE CODE:  NO

PEAK REFLOW TEMPERATURE (CEL):  NOT SPECIFIED

PIN COUNT:  40

POWER SUPPLIES:  5 V

PROGRAMMABLE LOGIC TYPE:  OT PLD

PROPAGATION DELAY:  33 NS

QUALIFICATION STATUS:  NOT QUALIFIED

SEATED HEIGHT-MAX:  4.826 MM

SUBCATEGORY:  PROGRAMMABLE LOGIC DEVICES

SUPPLY VOLTAGE-MAX:  5.25 V

SUPPLY VOLTAGE-MIN:  4.75 V

SUPPLY VOLTAGE-NOM:  5 V

SURFACE MOUNT:  NO

TECHNOLOGY:  CMOS

TEMPERATURE GRADE:  COMMERCIAL

TERMINAL FINISH:  TIN/LEAD (SN/PB)

TERMINAL FORM:  THROUGH-HOLE

TERMINAL PITCH:  2.54 MM

TERMINAL POSITION:  DUAL

TIME@PEAK REFLOW TEMPERATURE-MAX (S):  NOT SPECIFIED

WIDTH:  15.24 MM