ADDITIONAL FEATURE:  REGISTER PRELOAD; POWER-UP RESET

ARCHITECTURE:  PAL-TYPE

CLOCK FREQUENCY-MAX:  62.5 MHZ

JESD-30 CODE:  R-PDIP-T24

JESD-609 CODE:  E0

LENGTH:  31.855 MM

MANUFACTURER:  LATTICE SEMICONDUCTOR CORPORATION

MANUFACTURER PART NUMBER:  GAL20XV10B-15LP

NUMBER OF DEDICATED INPUTS:  10

NUMBER OF I/O LINES:  10

NUMBER OF INPUTS:  20

NUMBER OF OUTPUTS:  10

NUMBER OF PRODUCT TERMS:  40

NUMBER OF TERMINALS:  24

OPERATING TEMPERATURE-MAX:  75 °C

OPERATING TEMPERATURE-MIN:  0 °C

ORGANIZATION:  10 DEDICATED INPUTS, 10 I/O

OUTPUT FUNCTION:  MACROCELL

PACKAGE BODY MATERIAL:  PLASTIC/EPOXY

PACKAGE CODE:  DIP

PACKAGE DESCRIPTION:  DIP, DIP24,.3

PACKAGE EQUIVALENCE CODE:  DIP24,.3

PACKAGE SHAPE:  RECTANGULAR

PACKAGE STYLE:  IN-LINE

PART PACKAGE CODE:  DIP

PIN COUNT:  24

POWER SUPPLIES:  5 V

PROGRAMMABLE LOGIC TYPE:  EE PLD

PROPAGATION DELAY:  15 NS

QUALIFICATION STATUS:  NOT QUALIFIED

SEATED HEIGHT-MAX:  4.57 MM

SUBCATEGORY:  PROGRAMMABLE LOGIC DEVICES

SUPPLY VOLTAGE-MAX:  5.25 V

SUPPLY VOLTAGE-MIN:  4.75 V

SUPPLY VOLTAGE-NOM:  5 V

SURFACE MOUNT:  NO

TECHNOLOGY:  CMOS

TEMPERATURE GRADE:  COMMERCIAL EXTENDED

TERMINAL FINISH:  TIN/LEAD (SN85PB15)

TERMINAL FORM:  THROUGH-HOLE

TERMINAL PITCH:  2.54 MM

TERMINAL POSITION:  DUAL

WIDTH:  7.62 MM