ADDITIONAL FEATURE:  3-2-2-3 INPUT

FAMILY:  LS

JESD-30 CODE:  R-PDIP-T14

JESD-609 CODE:  E0

LENGTH:  18.86 MM

LOAD CAPACITANCE (CL):  15 PF

LOGIC IC TYPE:  AND-OR-INVERT GATE

MANUFACTURER:  MOTOROLA SEMICONDUCTOR PRODUCTS

MANUFACTURER PART NUMBER:  SN74LS54N

MAX I(OL):  8 MA

NUMBER OF FUNCTIONS:  1

NUMBER OF INPUTS:  10

NUMBER OF TERMINALS:  14

OPERATING TEMPERATURE-MAX:  70 °C

OPERATING TEMPERATURE-MIN:  0 °C

PACKAGE BODY MATERIAL:  PLASTIC/EPOXY

PACKAGE CODE:  DIP

PACKAGE DESCRIPTION:  DIP, DIP14,.3

PACKAGE EQUIVALENCE CODE:  DIP14,.3

PACKAGE SHAPE:  RECTANGULAR

PACKAGE STYLE:  IN-LINE

PEAK REFLOW TEMPERATURE (CEL):  NOT SPECIFIED

POWER SUPPLIES:  5 V

POWER SUPPLY CURRENT-MAX (ICC):  2 MA

PROP. DELAY@NOM-SUP:  20 NS

PROPAGATION DELAY (TPD):  20 NS

QUALIFICATION STATUS:  NOT QUALIFIED

SCHMITT TRIGGER:  NO

SEATED HEIGHT-MAX:  4.69 MM

SUBCATEGORY:  GATES

SUPPLY VOLTAGE-MAX (VSUP):  5.25 V

SUPPLY VOLTAGE-MIN (VSUP):  4.75 V

SUPPLY VOLTAGE-NOM (VSUP):  5 V

SURFACE MOUNT:  NO

TECHNOLOGY:  TTL

TEMPERATURE GRADE:  COMMERCIAL

TERMINAL FINISH:  TIN/LEAD (SN/PB)

TERMINAL FORM:  THROUGH-HOLE

TERMINAL PITCH:  2.54 MM

TERMINAL POSITION:  DUAL

TIME@PEAK REFLOW TEMPERATURE-MAX (S):  NOT SPECIFIED

WIDTH:  7.62 MM